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PIC32MX3XX/4XX
14.0
TIMERS 2, 3, 4, 5
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
Note 1: This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
The 32-bit timers can operate in three modes:
? Synchronous Internal 32-bit Timer
? Synchronous Internal 32-bit Gated Timer
? Synchronous External 32-bit Timer
Section 14. “Timers” (DS61105) of the
“PIC32MX Family Reference Manual” ,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
Note:
14.1
Throughout this chapter, references to
registers TxCON, TMRx and PRx use ‘x’
to represent Timer2 through 5 in 16-bit
modes. In 32-bit modes, ‘x’ represents
Timer2 or 4; ‘y’ represents Timer3 or 5.
Additional Supported Features
“Memory Organization” in this data
sheet for device-specific register and bit
information.
This family of PIC32MX devices features four
synchronous 16-bit timers (default) that can operate as
a free-running interval timer for various timing applica-
tions and counting external events. The following
modes are supported:
? Synchronous Internal 16-bit Timer
? Synchronous Internal 16-bit Gated Timer
? Synchronous External 16-bit Timer
? Selectable clock prescaler
? Timers operational during CPU Idle
? Time base for input capture and output compare
modules (Timer2 and Timer3 only)
? ADC event trigger (Timer3 only)
? Fast bit manipulation using CLR, SET and INV
registers
FIGURE 14-1:
TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)
TMRx
Sync
ADC Event
Trigger (1)
Equal
Comparator x 16
PRx
Reset
TxIF
Event Flag
0
1
TGATE (TxCON<7>)
Q
Q
D
TGATE (TxCON<7>)
TCS (TxCON<1>)
ON (TxCON<15>)
TxCK (2)
x1
Note 1: ADC event trigger is available on Timer3 only.
2: TxCK pins not available on 64-pin devices.
? 2010 Microchip Technology Inc.
Gate
Sync
PBCLK
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS (TxCON<6:4>)
DS61143G-page 105
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